1. Field of the Invention
This invention relates generally to the field of computing technology and more particularly concerns optimal methods for electroplating copper interconnects.
2. Description of the Related Art
In most existing IC structures, the speed at which a signal can be transmitted along an interconnect of length L is limited by the time constant of approximately RCL2 where R is the resistance and C the capacitance of the interconnect, both per unit length. Exemplary figures of existing IC structures may be found in IEEE Trans. Electron Devices, ED-32 (5), pp. 903-909 (1985) written by H. B. Bakoglu and J. D. Meindl. This reference is incorporated by reference.
To obtain signal transit at light speeds, an electrical transmission line should be used. This is a well controlled interconnect with the property that the series resistance RL is much less than the intrinsic impedance defined as {square root over ((L/C))} where L is the inductance and C the capacitance of the structure, per unit length. The design of such lines may assume that the surrounding wiring structures constitute an effective ground, or shielding structures may be employed (such as dedicated power line planes decoupled well to ground), or more specialized structures such as a coplanar waveguide can be used. The speed of propagation of an electrical signal in such a line is 1{square root over (L/C)}, the speed of light in the surrounding dielectric.
Unfortunately, the intrinsic impedance Z of such lines cannot exceed approximately 376 ohms in free space, or 248 ohms in a dielectric with dielectric constant 2.3 (at the frequency of interest). A typical value would be 25-100 ohms. Because of this, the line length that can satisfy the equation RL less than Z is increasingly limited as one proceeds to smaller wire dimensions. In a wire with 1 micron side, made of copper and operating at a low frequency, R is 198 ohms/cm. At higher frequencies, around 10 GHz, skin effects in the wire increase this value. Clearly the dimension of the wire must be increased if the RC delay is to be avoided, or the length of the line must be kept short. At present, a common solution to the RC delays is to add repeaters along the wire at intervals short enough that the transit time is kept well under 1/(RCL2). This has the disadvantage that quite large transistors are needed to drive the lines, which use valuable die area. Also, contacts must be made through the entire metallization stack, with low resistance, to these transistors, which leads to xe2x80x98via blockagexe2x80x99, a name referring to the restrictions on wire routing in the intervening layers that is caused by the contact via. Furthermore each repeater introduces a propagation delay. The power drawn by the large number of repeaters is also a concern. It would be desirable if line delays could be reduced by the use of large enough wires that RL can be kept below Z for a substantial wire length.
FIG. 1 shows a graph 20 illustrating line resistance per cm for various signal frequencies with a square copper wire of sensitivity 2.0 xcexcxcexa9cm and indicates the approximate resistance per cm of square sectioned copper wires of various dimensions. Graph 20 has plots 22, 24, 26, 28, and 30 of line resistance per cm for signal frequencies, 1 GHz, 3 GHz, 10 GHz, 30 GHz, and 100 GMz respectively. For a die of 25 mm per side, consistent with future die sizes in high performance applications, the Manhattan distance from corner to corner is 5 cm. The Manhattan distance is the shortest distance between two points along a rout that is constrained to run only in two predefined orthogonal directions (usually parallel to the edges of the die). An unrepeatered line for this length, to run at 3 GHz signal frequency, should be at least 5 microns on a side in order for signals to pass at the speed of light in the dielectric. In FIG. 1 it has been, assumed that for adequate signal transmission the wire should obey the rule RL less than Z at three times the signal frequency.
Existing IC manufacturing techniques are poorly suited to production of such wires. The usual process for deposition of finer copper line structures (up to about 1.0 micron) uses the xe2x80x98damascenexe2x80x99 technique. To deposit a damascene wire, a trench is first etched, a thin barrier layer is applied, and then a xe2x80x98seed layerxe2x80x99, usually of copper and always of a good conductor, is deposited. The entire wafer is then electroplated. The wafer is then chemomechanically polished until all the overlying copper is removed and an inlaid copper line remains.
Unfortunately most plating techniques deposit a layer of metal in the field whose thickness is on the same order of the depth of the trench. In the case of a thick line, all of this material must be removed in a uniform manner. This is a time consuming and wasteful process.
The deposition of copper lines with widths of 100 microns and above is generally done by a subtractive process in which a thin continuous copper line is deposited, a resist is applied and patterned, and a wet etch process used to pattern the wires. Unfortunately this technique loses its usefulness for wires with height close to their width because of undercutting by the isotropic etch. This undercutting can be alleviated by electrochemical etching but this is a difficult process. Such an exemplary process is described by M. Datta in IBM J. Res. Develop. 42 (5) pp. 655-669 (1998). This document is hereby incorporated by reference.
Furthermore the pitch of such wiring is severely restricted, and the resists common used perform poorly at feature sizes on the order of 10 microns. For on-die interconnects the wires are required to have aspect ratio (height/width) of one and above in order to reduce capacitance and allow for enough individual interconnections.
Plating of lines of 10-100 micron linewidth can be done by xe2x80x98through-maskxe2x80x99 plating. An exemplary through-mask process may be seen in S. Krongelb, L. T. Romankiw, and J. A. Tornello, Id. p. 575-585 (1998). A dielectric is coated with adhesion and seed layers; resist is then applied, exposed, and developed to leave the regions where plating is to occur exposed. The seed layer is attached to the negative terminal of an electrochemical cell and copper is electroplated. It will deposit only in the regions not covered by the resist. Unfortunately such a technique is time consuming. This is because the plating rate of the lines is strongly dependent upon the local pattern density, that is the fraction of area not covered by copper. This non-uniformity is increased as the plating current increases, which means that the current cannot be increased to allow faster plating when thick lines are needed; in fact the current density must generally be reduced, leading to a superlinear dependence of plating time on wire thickness. This pattern dependence exists in damascene processing but is much less pronounced. Through-mask processes would be economical for wafer processing only when large batches of wafers were coated in an inexpensive tool, because of the time needed for plating, but unfortunately, tools for electroplating semiconductor wafers are costly. Following the plating process the resist is stripped and the seed and adhesion layers removed, usually by wet etch. In all of these wet processes, backside wafer contamination with copper will occur unless specialized equipment is used or the rear of the wafer is protected in some way. Backside contamination is bad because if the copper contamination migrates to the transistor junctions the junctions will be destroyed.
In view of the above, a technique which enables more effective and less time consuming plating of wafers while reducing or even eliminating the CMP process is needed.
Broadly speaking, the present invention fills these needs by providing a method for more effective plating of wafers while reducing or even eliminating the CMP process. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment a method for forming conductive features in dielectric materials is disclosed which includes providing a dielectric layer and forming a release layer over the dielectric layer. Then a feature is defined into the each of the release layer and the dielectric layer and a conductive material is filled over the release layer and into the feature. The release layer is then removed where the removing serves to remove the conductive material from over the dielectric layer previously covered by the release layer.
In another embodiment, a method for electroplating copper interconnects in a dielectric layer is provided which includes forming a release layer over the dielectric layer and patterning the release layer to form an exposed outline of a feature over the dielectric layer. Then the dielectric layer is etched in the exposed outline of the feature where the etching is defined at least partially into the dielectric layer to define an etched feature. The method also includes blanket lining the release layer and the dielectric layer where the blanket lining covers the release layer and the etched feature. Then the method applies a copper material over the blanket lining and into the etched feature. The release layer is then dissolved where the dissolving removes the blanket lining and the copper material from over the dielectric layer, while leaving the copper material in the etched feature.
In another embodiment, a method for forming a conductive feature in a photo-sensitive dielectric material is provided which includes applying a photo-sensitive release layer over the photo-sensitive dielectric material and exposing the photo-sensitive release layer and the photo-sensitive dielectric material so as to define a feature into the photo-sensitive dielectric material. The method also includes developing the photo-sensitive release layer and the photo-sensitive dielectric material so as to define the feature. Then the feature is filled with a conductive material. The release layer is then removed so as to remove the conductive material from over regions other than in the feature.
In yet another embodiment, a method for electroplating copper interconnects is provided which includes generating a stack including a first dielectric layer, a second dielectric layer and a release layer. The method also includes etching away a portion of the release layer and the second dielectric layer exposing a trench through to the first dielectric layer. Then the method applies a barrier layer, a seed layer, and a conformal dielectric layer on the stack after the etching. A portion of the conformal dielectric layer on horizontal surfaces of the stack is then removed. Copper is then plated onto the stack thereby filling the trench with the copper. The method further includes removing the release layer where the removing detaches materials above the release layer from the stack.
The advantages of the present invention are numerous. Most notably, unlike pattern plating, this process is relatively insensitive to pattern density, and may therefore be possible to utilize this process in existing wafer plating tools. In addition, throughput may be greatly increased Optimally, either no CMP or minimal CMP is generally necessary because the process uses a single lithographic exposure, and does not require additional steps to strip the dielectric, remove the seed layer, and replace the dielectric, which are all steps needed by the through-mask plating process. This should lead to considerable cost reduction.
The production of solid copper waste as a result of the lift-off step can be removed from the process liquids readily as opposed to the accumulation of greater bulk of the waste CMP slurry that would be a by-product of a CMP process. Additionally, the heavy metal contaminated wash produced by the need to strip the seed layer (as in through-mask plating) is not produced in the present invention. In addition, it is anticipated that the chemistry to be used will be inexpensive compared with that used for plating small, high aspect ratio, features. Although the process described relates to the filling of a single trench, there is no reason that this process cannot be used for structures such as interlevel vias. It may also be extended to xe2x80x98dual damascenexe2x80x99 processing in which the via and line are plated at the same time.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.